Vathys is hiring a packaging engineer to develop our 3D integration flow for a novel processor that co-designs architecture and 3D integration to deliver unprecedented performance for machine learning workloads.
You will be in charge of developing the 3D packaging flow which will involve die placement and alignment as well as the fabrication of various connections, such as those used for power and I/O.
In addition, you will interface with the architects and design team in order to ensure that the chip works around the limitations of the process flow.
Location is ideally in the Bay Area, but remote is also possible if there is a nanofabrication facility (e.g. an university lab) nearby.
Generous compensation will be provided to the right talent.
Please contact tapabrata_ghosh[at]vathys[dot]ai if you’re interested.
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